[OpenBIOS] [commit] r1143 - trunk/openbios-devel/drivers
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svn at openbios.org
Sun Jun 9 14:25:09 CEST 2013
Author: mcayland
Date: Sun Jun 9 14:25:08 2013
New Revision: 1143
URL: http://tracker.coreboot.org/trac/openbios/changeset/1143
Log:
pci: Modify PCI display devices so that open and close words are not created
automatically during initialisation.
This is because the work needs to be done by the "is-install" word as per the
IEEE1275 specification.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland at ilande.co.uk>
Modified:
trunk/openbios-devel/drivers/pci.c
trunk/openbios-devel/drivers/pci.h
Modified: trunk/openbios-devel/drivers/pci.c
==============================================================================
--- trunk/openbios-devel/drivers/pci.c Sun Jun 9 14:25:03 2013 (r1142)
+++ trunk/openbios-devel/drivers/pci.c Sun Jun 9 14:25:08 2013 (r1143)
@@ -44,6 +44,7 @@
DECLARE_UNNAMED_NODE( ob_pci_bus_node, INSTALL_OPEN, 2*sizeof(int) );
DECLARE_UNNAMED_NODE( ob_pci_simple_node, INSTALL_OPEN, 2*sizeof(int) );
+DECLARE_UNNAMED_NODE( ob_pci_empty_node, 0, 2*sizeof(int) );
const pci_arch_t *arch;
@@ -342,6 +343,10 @@
{ "close", ob_pci_close },
};
+NODE_METHODS(ob_pci_empty_node) = {
+ { NULL, ob_pci_initialize }
+};
+
static void pci_set_bus_range(const pci_config_t *config)
{
phandle_t dev = find_dev(config->path);
@@ -1229,6 +1234,9 @@
REGISTER_NAMED_NODE_PHANDLE(ob_pci_bus_node, config.path, phandle);
}
break;
+ case PCI_CLASS_DISPLAY:
+ REGISTER_NAMED_NODE_PHANDLE(ob_pci_empty_node, config.path, phandle);
+ break;
default:
REGISTER_NAMED_NODE_PHANDLE(ob_pci_simple_node, config.path, phandle);
break;
Modified: trunk/openbios-devel/drivers/pci.h
==============================================================================
--- trunk/openbios-devel/drivers/pci.h Sun Jun 9 14:25:03 2013 (r1142)
+++ trunk/openbios-devel/drivers/pci.h Sun Jun 9 14:25:08 2013 (r1143)
@@ -27,6 +27,7 @@
#define PCI_REVISION_ID 0x08 /* Revision ID */
+#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_PROG 0x09
#define PCI_CLASS_DEVICE 0x0a
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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